The present invention relates to a network processor in broadband internet devices, and more particularly to a network processor with a network address translation (NAT) engine, i.e. a packet accelerator, for accelerating packet processing between different kinds of networking technologies, to reduced power consumption and reserve computing power for other networking applications.
With the rapid development of internet, there are more and more networking applications. Thus, the broadband gateways need to handle many kinds of packet processing via different types of networking technologies, e.g. Ethernet, xDSL (digital subscriber line), ATM (Asynchronous Transfer Mode), WLAN (wireless local area network), 3G/3.5G etc.) as well as the application protocols, e.g. VoIP (Voice over Internet Protocol), DLNA (Digital Living Network Alliance), OSGi (Open Service Gateway Initiative) etc.
Under such a situation, the network processor in the broadband gateway shall boost the performance for these demands. Increasing the Central Processing Unit (CPU) operation frequency is an intuitive approach to boost the network processor performance. However, the power consumption will increase a lot.
Besides, even with higher grade of CPU, the improvement ratio is not enough because of more and more computing power demand due to the above packet processing and applications. Moreover, a conventional packet offload engine only considers a single networking interface instead of different kinds of networking interfaces. Thus, there is a need to improve over the prior art.